DocumentCode
2756645
Title
Behavioural Modelling of DLLs for Fast Simulation and Optimisation of Jitter and Power Consumption
Author
Barajas, Enrique ; Mateo, Diego ; González, José Luis
Author_Institution
Electron. Eng. Dept., Univ. Politec. Catalunya, Barcelona, Spain
fYear
2010
fDate
1-3 Sept. 2010
Firstpage
541
Lastpage
547
Abstract
This paper presents a behavioural model for fast DLL simulations. The behavioural model includes a modelling of the various noise sources in the DLL that produce output jitter. The model is used to obtain the dependence of the output jitter versus the power consumption. The model exploits the open-loop DLL analysis to reduce simulation time when compared to typical DLL evaluation.
Keywords
delay lock loops; jitter; logic design; DLL behavioural modelling; delay-lock loops; jitter optimisation; open-loop DLL analysis; power consumption; Analytical models; Charge pumps; Delay; Jitter; Noise; Transistors; Voltage control; CMOS; DLL; Verilog-A; behavioural; modelling; optimisation;
fLanguage
English
Publisher
ieee
Conference_Titel
Digital System Design: Architectures, Methods and Tools (DSD), 2010 13th Euromicro Conference on
Conference_Location
Lille
Print_ISBN
978-1-4244-7839-2
Type
conf
DOI
10.1109/DSD.2010.86
Filename
5615551
Link To Document