Title :
Behavioural Modelling of DLLs for Fast Simulation and Optimisation of Jitter and Power Consumption
Author :
Barajas, Enrique ; Mateo, Diego ; González, José Luis
Author_Institution :
Electron. Eng. Dept., Univ. Politec. Catalunya, Barcelona, Spain
Abstract :
This paper presents a behavioural model for fast DLL simulations. The behavioural model includes a modelling of the various noise sources in the DLL that produce output jitter. The model is used to obtain the dependence of the output jitter versus the power consumption. The model exploits the open-loop DLL analysis to reduce simulation time when compared to typical DLL evaluation.
Keywords :
delay lock loops; jitter; logic design; DLL behavioural modelling; delay-lock loops; jitter optimisation; open-loop DLL analysis; power consumption; Analytical models; Charge pumps; Delay; Jitter; Noise; Transistors; Voltage control; CMOS; DLL; Verilog-A; behavioural; modelling; optimisation;
Conference_Titel :
Digital System Design: Architectures, Methods and Tools (DSD), 2010 13th Euromicro Conference on
Conference_Location :
Lille
Print_ISBN :
978-1-4244-7839-2
DOI :
10.1109/DSD.2010.86
