DocumentCode
2756677
Title
Synthesis of controllers for full testability of integrated datapath-controller pairs
Author
Carletta, Joan ; Nourani, Mehrdad ; Papachristou, Christos
Author_Institution
Dept. of Comput. Eng. & Comput. Sci., Case Western Reserve Univ., Cleveland, OH, USA
fYear
1999
fDate
9-12 March 1999
Firstpage
278
Lastpage
282
Abstract
This work facilitates the testing of datapath-controller pairs in an integrated fashion, with datapath and controller tested together in a single test session. Such an approach requires less test overhead than an approach that isolates datapath and controller from each other during test. The ability to do an integrated test is especially important when testing core-based embedded systems. The key to the approach is a careful examination of the relationship between techniques for controller synthesis and the types of gate level controller faults that can occur. A method for controller synthesis is outlined that results in a fully testable controller, so that full fault coverage of the controller can be achieved without any need for isolation during test.
Keywords
binary decision diagrams; data flow graphs; design for testability; embedded systems; finite state machines; high level synthesis; logic testing; controllers synthesis; core-based embedded systems; data flow graph; finite state machine; full fault coverage; full testability; gate level controller faults; high level synthesis; integrated datapath-controller pairs; single test session; state diagram; stuck-at-faults; Binary decision diagrams; Control system synthesis; Control systems; Degradation; Flow graphs; Hardware; Logic testing; Multiplexing; Registers; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe Conference and Exhibition 1999. Proceedings
Conference_Location
Munich, Germany
Print_ISBN
0-7695-0078-1
Type
conf
DOI
10.1109/DATE.1999.761134
Filename
761134
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