Systolic array building blocks for real-time signal processing

The authors describe the application of a number of contrasting module designs to adaptive processing systems. In particular, they illustrate that, whereas the transputer can effectively implement complex parallel algorithms designed for audio band problems similar algorithms for RF antenna array processing have demanded the development of a special DSP chip offering a much higher processing throughput performance. They describe a transputer implementation of an acoustic adaptive beamformer and a special Node Chip implementation of a radio frequency adaptive beamformer. The implementation of this 4-channel adaptive array module (4-ASAM) required a 2 MHz bandwidth and 300 MFLOPS of processing power