Reasoning about VHD3L and VHDL-AMS using denotational semantics

This paper introduces a denotational semantics for a core of the draft IEEE standard analog and mixed signal design language VHDL-AMS, and derives general results about the behaviour of VHDL-AMS programs from it. We include, for example, a demonstration that VHDL-AMS parallelism is benign in the absence of shared initializations. As proof of concept we have built an interpreted simulator that prototypes the semantics and which runs multi-process mixed analog and digital descriptions correctly.