Design and technology challenges for sub-0.5 μm CMOS and bipolar

Author

Ning, Tak H.

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

1989

fDate

17-19 May 1989

Firstpage

307

Lastpage

311

Abstract

The design and technology problems that must be solved in order to realize the potential performance of sub-0.5-μm CMOS and bipolar devices are discussed. High-field and high-current-density effects are among the most important issues. The goal is to prevent these effects from becoming problems and yet achieve performance as expected from scaling. It is seen that there are no simple solutions. It is a matter of trading off performance with process complexity and/or reliability in an optimal manner. Scaling CMOS to about 50-nm channel length appears to be quite possible. However, scaling bipolar to much below 0.25 μm requires more understanding of the device physics and major technology breakthroughs

Keywords

CMOS integrated circuits; VLSI; bipolar integrated circuits; circuit reliability; integrated circuit technology; 50 nm; CMOS; bipolar devices; channel length; device physics; high-current-density effects; process complexity; reliability; scaling; CMOS technology; Current density; Diodes; Inverters; MOS devices; MOSFET circuits; Photonic band gap; Power MOSFET; Power supplies; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems and Applications, 1989. Proceedings of Technical Papers. 1989 International Symposium on

Conference_Location

Taipei

Type

conf

DOI

10.1109/VTSA.1989.68635

Filename

68635