Title :
Potentials of chip-package co-design for high-speed digital applications
Author :
Tröster, Gerhard
Author_Institution :
Electron. Lab., ETH Zurich, Switzerland
Abstract :
The inherent potentials of Si technology are limited by the low interaction with packaging. Co-design as the symbiosis between the ICs and appropriate high-density packaging offers lower RC line delay, improved SSN and lower costs compared to single-chip approaches. The distribution of the system functionality between ICs and the packaging level opens up new vistas in future electronic design and system architecture
Keywords :
delays; digital integrated circuits; high-speed integrated circuits; integrated circuit design; integrated circuit noise; integrated circuit packaging; RC line delay; SSN; chip-package co-design; costs; electronic design; high-density packaging; high-speed digital applications; single-chip approaches; system architecture; Bandwidth; Central Processing Unit; Clocks; Costs; Delay lines; Electronics packaging; Integrated circuit interconnections; Integrated circuit packaging; Semiconductor device packaging; Wiring;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition 1999. Proceedings
Conference_Location :
Munich
Print_ISBN :
0-7695-0078-1
DOI :
10.1109/DATE.1999.761159
