Title :
Weak Write Test Mode: an SRAM cell stability design for test technique
Author :
Meixner, Anne ; Banik, Jash
Author_Institution :
Intel Corp., Hillsboro, OR, USA
Abstract :
The detection of cell stability and data retention faults in SRAMs has been a time consuming process. In this paper we discuss a new design for test technique called Weak Write Test Mode (WWTM). This technique applies test circuitry which attempts to overwrite the data stored in SRAM cells. It is designed so that only defective cells are overwritren. The resulting test has a shorter test time and improved detection capability. In addition, WWTM has a low silicon area cost and no impact on product performance. Silicon results are reported
Keywords :
CMOS memory circuits; SRAM chips; automatic testing; design for testability; digital simulation; economics; elemental semiconductors; fault location; integrated circuit testing; silicon; SRAM cell stability; Si; Weak Write Test Mode; defective cells; design for test; detection capability; product performance; silicon area cost; test time; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Manufacturing; Random access memory; Read-write memory; Silicon; Solids; Stability;
Conference_Titel :
Test Conference, 1997. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-4209-7
DOI :
10.1109/TEST.1997.639732
