C1. Flexible LDPC decoder architecture for (3–6) regular codes

Low density parity check (LDPC) codes are a class of block codes with a very high error correcting performance. That performance made them suitable for many modern applications such as Digital Satellite Broadcasting system (DVB-S2), Wireless Local Area Network (IEEE 802.11n) and Metropolitan Area Network (802.16e). The decoding process of these codes is based on an iterative algorithm that requires many computational cycles. The implementation of a high performance flexible decoder that can support multiple codes is still an area of research. This paper presents a modified implementation technique of the normal sum-product decoding algorithm. That modification greatly enhances the performance of the decoding process to achieve high throughput. Furthermore, a flexible, partially parallel architecture that is tailored especially to support that modified implementation is given. The proposed LDPC decoder architecture is simulated on Xilinx ISE Simulator and implemented using VHDL code.