Title :
Full scan fault coverage with partial scan
Author :
Lin, Xijiang ; Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution :
Mentor Graphics Corp., Wilsonville, OR, USA
Abstract :
In this paper, a test generation based partial scan selection procedure is proposed. The procedure is able to achieve the same level of fault coverage as in a full scan design by scanning only a subset of the flip-flops. New measures are used to guide the flip-flop selection during the procedure. The proposed procedure is applied to the ISCAS-89 and the ADDENDUM-93 benchmark circuits. For all the circuits, it is possible to achieve the same fault coverage as that for full scan while scanning a portion of the flip-flops.
Keywords :
automatic testing; boundary scan testing; fault diagnosis; flip-flops; logic testing; sequential circuits; ADDENDUM-93 benchmark circuits; ISCAS-89 benchmark circuits; fault coverage; flip-flop selection; partial scan selection procedure; test generation; Automatic test pattern generation; Benchmark testing; Circuit faults; Circuit testing; Computational efficiency; Electrical fault detection; Fault detection; Fault diagnosis; Feedback loop; Sequential analysis;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition 1999. Proceedings
Conference_Location :
Munich, Germany
Print_ISBN :
0-7695-0078-1
DOI :
10.1109/DATE.1999.761167
