Title :
Digital MOS circuit partitioning with symbolic modeling
Author :
Xirgo, Lluís Ribas ; Bordoll, Jordi Carrabina
Author_Institution :
Dept. of Comput. Sci., Univ. Autonoma de Barcelona, Spain
Abstract :
This paper presents a method to automatically recognize and model singleand multi-output logic gates out of a switch-level network, even for irregular transistor structures. Resulting subcircuit models are directly used in a symbolic simulator for circuit analysis purposes. Other applications of derived netlists cover switch-level simulation acceleration and test generation tool enhancement.
Keywords :
MOS logic circuits; circuit simulation; integrated circuit modelling; logic gates; logic partitioning; logic simulation; symbol manipulation; circuit analysis; circuit partitioning; derived netlists; digital MOS circuit; irregular transistor structures; multi-output logic gates; single-output logic gates; subcircuit models; switch-level network; switch-level simulation acceleration; symbolic modeling; symbolic simulator; test generation tool enhancement; Analytical models; Circuit testing; Computer science; Delay; Electrical capacitance tomography; Flexible printed circuits; Logic devices; Logic testing; National electric code; Switches;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition 1999. Proceedings
Conference_Location :
Munich, Germany
Print_ISBN :
0-7695-0078-1
DOI :
10.1109/DATE.1999.761173
