High speed GaAs subsystem design using feed through logic

Author

Montiel-Nelson, J.A. ; de Armas, V. ; Sarmiento, R. ; Nunez, A. ; Nooshabadi, S.

Author_Institution

Centre for Appl. Microelectron., Univ. of Las Palmas de Gran Canaria, Spain

fYear

1999

fDate

1999

Firstpage

509

Lastpage

513

Abstract

In this paper design of fast arithmetic circuits using a GaAs based feed through logic (FTL) family is presented. A modified version of FTL termed differential FTL (DFTL) is introduced and basic aspects of design methodologies using FTL are discussed. A 4-bit ripple-carry adder is designed and its performance is evaluated against other similar reported works in terms of device count, chip area, delay clock rate, and power consumption. It is shown how arithmetic circuits based on FTL outperform the evaluated performance. A 4-bit magnitude comparator is designed and performance evaluated against four cascaded 1-bit comparators

Keywords

III-V semiconductors; MESFET integrated circuits; adders; comparators (circuits); delays; digital arithmetic; field effect logic circuits; gallium arsenide; high-speed integrated circuits; integrated circuit design; 4 bit; GaAs; arithmetic circuits; chip area; delay clock rate; design methodologies; device count; differential FTL; feed through logic family; high speed subsystem design; magnitude comparator; power consumption; ripple-carry adder; Adders; Arithmetic; Clocks; Delay; Design methodology; Feeds; Gallium arsenide; Logic circuits; Logic design; Logic devices;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe Conference and Exhibition 1999. Proceedings

Conference_Location

Munich

Print_ISBN

0-7695-0078-1

Type

conf

DOI

10.1109/DATE.1999.761174

Filename

761174