Solder joint strain reduction of leadless IC packages through finite element analysis tailored PCB construction

Reducing the strain experienced by a solder joint is essential in proliferating the use of high-density, large-area leadless ceramic chip carriers for high I/O (>100) and area die. One of the most controllable variables affecting solder joint fatigue over temperature excursions is the in-plane shear strain, which results from the difference in thermal coefficient of expansion (TCE) between the ceramic chip carrier and the printed-circuit board (PCB). TCE tailoring of the PCB with embedded layers of copper-clad Invar restraining laminates necessitates a refined analytical method for predicting PCB/soldering interface TCE. Finite-element analysis (FEA) has been carried out, focusing on the distance of the laminate from the z-axis centerline. This FEA uses the shear and bulk modulus (Poisson´s ratio) of the PCB (epoxy-glass) and copper clad Invar to study the differential movement of an unpopulated board surface with temperature. The author presents FEA methods and results that are intended to assist future designs of controlled surface TCE circuit boards. He explores the ideal properties for a PCB laminate coupled with restraining laminates to effect higher reliability solder joints on large-area, leadless, ceramic IC packages