Defect-oriented mixed-level fault simulation of digital systems-on-a-chip using HDL

The validation of high-quality tests requires Defect-Oriented (DO) fault simulation. The purpose of this paper is to propose a methodology for mixed-level DO fault simulation, using HDL. A novel tool, veriDOFS, is introduced. Structural zooming is performed only for the system module in which the faults are injected. Verilog models for bridging and line open defects are proposed for intra-gate and inter-gate faults. Design hierarchy is exploited by pre-computing a test view of each cell in a library. The good trade-off accuracy/tractability, as well as the computational efficiency of the new tool are demonstrated by means of structural benchmarks up to 100,000 transistors and 300,000 realistic faults