Title :
Industrial evaluation of DRAM tests
Author :
Van De Goer, A.J. ; de Neef, J.
Author_Institution :
Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
Abstract :
This paper presents the results of 44 well known memory tests applied to 1896 1M*4 DRAM chips, using up to 96 different stress combinations with each test. The results show the importance of selecting the right stress combination, and that the theoretically better tests (i.e. those covering different functional faults) also have a higher fault coverage. However the currently used fault models still leave much to be explained; e.g., the used data backgrounds and address orders show an unexplainable large variation in fault coverage.
Keywords :
DRAM chips; automatic testing; fault diagnosis; integrated circuit testing; DRAM tests; address orders; fault coverage; functional faults; memory tests; stress combinations; used data backgrounds; Computer architecture; Electronic switching systems; Hip; Indium phosphide; Information technology; Leakage current; Postal services; Random access memory; Stress; Testing;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition 1999. Proceedings
Conference_Location :
Munich, Germany
Print_ISBN :
0-7695-0078-1
DOI :
10.1109/DATE.1999.761194
