Comparative ADC performance evaluation using a new emulation model for flash ADC architectures

Author

Wagdy, Mahmoud Fawzy ; Xie, Qiong

Author_Institution

Dept. of Electr. Eng., California State Univ., Long Beach, CA, USA

Volume

2

fYear

1994

fDate

3-5 Aug 1994

Firstpage

1159

Abstract

This paper investigates various flash A/D converters (ADC´s) using a new emulation model which mimics the gate-level architecture of a flash ADC with any number of bits, n. The model is used for studying the effects of noise and offset voltages at the comparator inputs on the ADC output deviation using a mean-square error criterion. The first ADC investigated is the full-flash one, which is compared with the successive-approximation ADC for the same n. Then, two-step flash ADC´s (i.e. half-flash) are investigated, with and without an interstage gain. Finally, error correction is attempted in conjunction with the later half-flash type

Keywords

analogue-digital conversion; circuit noise; error correction; comparator; emulation model; error correction; flash A/D converters; full-flash ADC; gate-level architecture; half-flash ADC; interstage gain; mean-square error; noise; offset voltage; performance evaluation; successive-approximation ADC; two-step flash ADC; Circuits; Clocks; Emulation; Error correction; Hardware; Logic; Performance gain; Radar applications; Video signal processing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1994., Proceedings of the 37th Midwest Symposium on

Conference_Location

Lafayette, LA

Print_ISBN

0-7803-2428-5

Type

conf

DOI

10.1109/MWSCAS.1994.519016

Filename

519016