QoR Analysis of Automated Clock-Mesh Implementation under OCV Consideration

In ASICs with structure sizes of 65nm and below the requirements of precise and robust clock networks continuously increase. High-speed circuits already use full-custom clock-meshes instead of buffer trees. Recently new clock-mesh synthesis tools with more automation have become available which better suit ASIC design flows. This paper provides a QoR analysis of these meshes versus highly optimized buffer trees with respect to timing and power. Furthermore, we analyzed the sensitivity of the topologies to OCV. For this purpose we realized a Monte Carlo analysis in SPICE as basis for STA. A design-dependent evaluation has been performed by applying the clock networks and analysis to six different designs. Independent of OCV, the clock-mesh reduces the global skew by up to 65% at the expense of a medial increase in average power consumption by 57% when compared to the buffer tree. Focussing on a further reduction of power dissipation, possible improvements of the automated clock-mesh implementation are proposed.