Title :
Symmetric transparent BIST for RAMs
Author :
Yarmolik, V.N. ; Hellebrand, S.
Author_Institution :
Dept. of Comput. Syst., Belarussian State Univ. of Inf. & Radioelectron., Minsk, Russia
Abstract :
The paper introduces the new concept of symmetric transparent BIST for RAMs. This concept allows one to skip the signature prediction phase of conventional transparent BIST approaches and therefore yields a significant reduction of test time. The hardware cost and the fault coverage of the new scheme remain comparable to that of a traditional transparent BIST scheme. In many cases, experimental studies even show a higher fault coverage obtained in shorter test time.
Keywords :
built-in self test; fault diagnosis; integrated circuit testing; integrated memory circuits; random-access storage; fault coverage; hardware cost; symmetric transparent BIST; test time reduction; Built-in self-test; Computer aided instruction; Computer architecture; Costs; Embedded computing; Hardware; Informatics; Random access memory; Read-write memory; System testing;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition 1999. Proceedings
Conference_Location :
Munich, Germany
Print_ISBN :
0-7695-0078-1
DOI :
10.1109/DATE.1999.761206
