DocumentCode
2758057
Title
Image convolution on FPGAs: the implementation of a multi-FPGA FIFO structure
Author
Benedetti, Arrigo ; Prati, Andrea ; Scarabottolo, Nello
Volume
1
fYear
1998
fDate
25-27 Aug 1998
Firstpage
123
Abstract
We present an implementation of a real time convolver, based on field programmable gate arrays (FPGAs) to perform the convolution operations. Main characteristics of the proposed approach are the usage of external memory to implement a FIFO buffer where incoming pixels are stored and the partitioning of the convolution matrix among several FPGAs, in order to allow data parallel computation and to increase the size of the convolution kernel
Keywords
buffer storage; convolution; field programmable gate arrays; image processing; image processing equipment; parallel programming; FIFO buffer; convolution kernel; convolution matrix; convolution operations; data parallel computation; external memory; field programmable gate arrays; image convolution; incoming pixels; multi FPGA FIFO structure; real time convolver; Buffer storage; Convolution; Delay; Field programmable gate arrays; Flip-flops; Image processing; Kernel; Pipelines; Pixel; Random access memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Euromicro Conference, 1998. Proceedings. 24th
Conference_Location
Vasteras
ISSN
1089-6503
Print_ISBN
0-8186-8646-4
Type
conf
DOI
10.1109/EURMIC.1998.711786
Filename
711786
Link To Document