Illegal state space identification for sequential circuit test generation

Author

Konijnenburg, M.H. ; Van der Linden, J. Th ; van de Goor, A.J.

Author_Institution

Fac. of Infl Technol. & Syst., Delft Univ. of Technol., Netherlands

fYear

1999

fDate

9-12 March 1999

Firstpage

741

Lastpage

746

Abstract

Here our new techniques are proposed to expand the known Global Illegal State (GIS) space, in order to reduce the search space. These techniques use the known GISes to generate candidate GISes, which have to be proven unjustifiable. This is an effective method to improve STPG performance because the number of stored GISes is reduced, saving memory and CPU time, while covering a larger part of the GIS space. To accelerate GIS space identification, we propose the legal state cache, to avoid useless justification repetitions. A data-structure is proposed to reduce the memory usage of the (G)ISes up to 10 times, and to accelerate GIS usage. Experimental results show a significant improvement in fault efficiency and CPU usage.

Keywords

automatic test pattern generation; cache storage; circuit analysis computing; data structures; flip-flops; identification; integrated circuit testing; integrated logic circuits; logic testing; sequential circuits; state-space methods; ATPG; CPU usage reduction; data structure; fault efficiency; global illegal state space; illegal state space identification; legal state cache; memory usage reduction; search space reduction; sequential circuit test generation; Central Processing Unit; Circuit faults; Circuit testing; Geographic Information Systems; Sequential analysis; Sequential circuits; Space technology; State-space methods; Synchronous generators; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe Conference and Exhibition 1999. Proceedings

Conference_Location

Munich, Germany

Print_ISBN

0-7695-0078-1

Type

conf

DOI

10.1109/DATE.1999.761213

Filename

761213