Hot-carrier reliability in submicron pMOSFETs

Degradation of device characteristics due to hot-carrier injection in submicron pMOSFETs (p-metal-oxide-semiconductor field-effect transistors) is discussed. pMOSFETs suffer significantly from enhanced device degradation in the submicron range due to the hot-electron-induced-punchthrough (HEIP) effect, the swapped pulse stress, and the gate-induced drain leakage current. As a result, the hot-carrier lifetime of pMOSFETs becomes shorter than that of LDD (lightly doped drain) nMOSFETs. Therefore, use of the LDD structure is essential in submicron pMOSFETs at 50 V supply voltage. The use of surface-channel pMOSFETs with p⁺ poly gate would mitigate the hot-carrier-induced device degradation if problems inherent to p⁺ poly gate were solved. The use of a gate-drain-overlapped LDD structure might become necessary in sub-half-micron pMOSFETs to improve the hot-carrier reliability without sacrificing the device performance