• DocumentCode
    2758351
  • Title

    Integrated resource assignment and scheduling of task graphs using finite domain constraints

  • Author

    Kuchcinski, Krzysztof

  • Author_Institution
    Dept. of Comput. & Inf. Sci., Linkoping Univ., Sweden
  • fYear
    1999
  • fDate
    9-12 March 1999
  • Firstpage
    772
  • Lastpage
    773
  • Abstract
    This paper presents an approach to modeling of task graphs using finite domain constraints. The synthesis of such models into an architecture consisting of microprocessors, ASICs and communication devices, is then defined as an optimization problem and it is solved using constraint solving techniques. The presented approach offers an elegant and powerful modeling technique for different architecture features as well as heterogeneous constraints. The extensive experimental results prove the feasibility of this approach.
  • Keywords
    application specific integrated circuits; circuit optimisation; constraint theory; data flow graphs; embedded systems; high level synthesis; resource allocation; scheduling; ASICs; architecture features; communication devices; constraint solving techniques; finite domain constraints; heterogeneous constraints; integrated resource assignment; microprocessors; modeling technique; optimization problem; scheduling; task graphs; Computer architecture; Cost function; Flow graphs; Heuristic algorithms; Information science; Labeling; Microprocessors; Pipeline processing; Processor scheduling; Prototypes;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation and Test in Europe Conference and Exhibition 1999. Proceedings
  • Conference_Location
    Munich, Germany
  • Print_ISBN
    0-7695-0078-1
  • Type

    conf

  • DOI
    10.1109/DATE.1999.761224
  • Filename
    761224