Title :
A fault list reduction approach for efficient bridge fault diagnosis
Author :
Wu, Jue ; Greenstein, Gary S. ; Rudnick, Elizabeth M.
Author_Institution :
Sun Microsyst., Menlo Park, CA, USA
Abstract :
A new fault list reduction approach is proposed for use in the first stage of a two-stage bridge fault diagnosis procedure. Modified structural analysis and layout extraction procedures are performed to obtain a reduced realistic bridge fault list that can be used in the second stage, which employs diagnostic fault simulation. The fault list reduction approach can reduce the final candidate bridge fault list by 92% to 99% compared with the diagnosis results achieved by the diagnostic fault simulator alone
Keywords :
VLSI; circuit analysis computing; combinational circuits; digital integrated circuits; failure analysis; fault diagnosis; fault simulation; integrated circuit testing; integrated logic circuits; logic testing; bridge fault diagnosis; diagnostic fault simulation; fault list reduction; layout extraction procedures; structural analysis; two-stage fault diagnosis procedure; Analytical models; Bridge circuits; Bridges; Circuit faults; Combinational circuits; Computational modeling; Fault diagnosis; Performance analysis; Software performance; Very large scale integration;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition 1999. Proceedings
Conference_Location :
Munich
Print_ISBN :
0-7695-0078-1
DOI :
10.1109/DATE.1999.761228
