Profile engineering for sub-micron CMOS using high energy ion implantation

Author

Stolmeijer, A. ; Pitt, M. ; Blanken, H. Den ; Van Der Plas, P. ; de Werdt, R.

Author_Institution

Philips Res. Lab., Eindhoven, Netherlands

fYear

1989

fDate

17-19 May 1989

Firstpage

317

Lastpage

320

Abstract

An improved implantation scheme has been developed for a submicron retrograde twin-well CMOS (complementary metal-oxide-semiconductor) process. A blanket p-well implantation is used to avoid one photoresist step. The use of a phosphorus compensating implantation for PMOS (p-channel MOS) transistor threshold voltage control avoids another resist step and photoresist processing on gate oxide. The latter results in an improved gate oxide integrity. The new implantation scheme has been successfully employed in the fabrication of a 1-Mb SRAM (static random-access memory) on 150-mm wafers

Keywords

CMOS integrated circuits; doping profiles; integrated circuit technology; integrated memory circuits; ion implantation; random-access storage; 1 Mbit; PMOS transistor threshold voltage control; SRAM; Si:P; blanket p-well implantation; gate oxide integrity; high energy ion implantation; profile engineering; static random-access memory; submicron retrograde twin-well CMOS; Boron; CMOS process; Implants; Impurities; Ion implantation; MOSFETs; Power engineering and energy; Random access memory; Resists; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems and Applications, 1989. Proceedings of Technical Papers. 1989 International Symposium on

Conference_Location

Taipei

Type

conf

DOI

10.1109/VTSA.1989.68637

Filename

68637