NES: the behavioral model for the formal semantics of a hardware design language UDL/I

Author

Ishiura, Nagisa ; Yasuura, Hiroto ; Yajima, Shuzo

Author_Institution

Dept. of Inf. Sci., Kyoto Univ., Japan

fYear

1990

fDate

24-28 Jun 1990

Firstpage

8

Lastpage

13

Abstract

A new behavioral model of hardware, the NES (nondeterministic event sequence) model, is described. It was developed for the purpose of defining formal semantics of the gate level and the register transfer level hardware description languages. The NES model is a generalization of event driven simulation and can be a basis of synthesis and verification as well as simulation. Basic concepts, formal definition, and a description method of the NES model are introduced

Keywords

VLSI; circuit CAD; logic CAD; specification languages; NES model; UDL/I; behavioral model; formal definition; formal semantics; gate level description; hardware design language; nondeterministic event sequence; register transfer level hardware description languages; simulation; synthesis; verification; Delay effects; Design automation; Design engineering; Discrete event simulation; Europe; Hardware design languages; Information science; Standardization; Standards development; Uncertainty;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1990. Proceedings., 27th ACM/IEEE

Conference_Location

Orlando, FL

ISSN

0738-100X

Print_ISBN

0-89791-363-9

Type

conf

DOI

10.1109/DAC.1990.114820

Filename

114820