DocumentCode
2758700
Title
Design-for-manufacturability (DFM) methodology and yield analysis for embedded RF circuits for system-in-package (SiP) applications
Author
Mukherjee, Souvik ; Swaminathan, Madhavan
Author_Institution
Georgia Inst. of Technol., Atlanta
fYear
2006
fDate
12-15 Dec. 2006
Firstpage
373
Lastpage
376
Abstract
The rapidly evolving telecommunications market has led to the need for advanced RF circuits. Complex multi-band/multi-mode RF designs require accurate prediction early in the design schedule and time-to-market pressures require that design iterations be kept to a minimum. This paper presents a layout-level, multi-domain DFM methodology and yield optimization technique for embedded RF circuits for SiP-based wireless applications. The proposed concept consists of layout- level statistical diagnosis and yield optimization. The statistical analysis takes into account the effect of the thermo-mechanical stress and the process variations that are incurred in batch fabrication. The results show good correlation with measurement/electromagnetic (EM) data.
Keywords
batch processing (industrial); design for manufacture; embedded systems; integrated circuit yield; optimisation; radiofrequency integrated circuits; statistical analysis; system-in-package; batch fabrication; design-for-manufacturability; embedded RF circuits; radiofrequency integrated circuits; statistical diagnosis; system-in-package; thermomechanical stress; yield optimization; Circuits; Design for manufacture; Design methodology; Fabrication; Optimization methods; Radio frequency; Statistical analysis; Thermal stresses; Thermomechanical processes; Time to market; Design-for-manufacturability (DFM); SiP; diagnosis; layout-level optimization; statistical analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
Microwave Conference, 2006. APMC 2006. Asia-Pacific
Conference_Location
Yokohama
Print_ISBN
978-4-902339-08-6
Electronic_ISBN
978-4-902339-11-6
Type
conf
DOI
10.1109/APMC.2006.4429442
Filename
4429442
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