Impact of low K dielectrics on microelectronics reliability

Rapid progress in CMOS transistor technology leading to the gigahertz speeds common today has necessitated major changes in semiconductor manufacturing technology and the development of high frequency compatible packaging. Modern microcircuits may have eight metal layers, each separated by only 0.1 micrometers. RC delays and cross talk rather than transistor speed are now the major performance limitations. The semiconductor industry has responded by developing copper metallization to replace aluminum and lower dielectric constant materials to replace silicon oxide. Within the last decade the industry has shifted from fully integrated production to the fabless model of IC manufacture for all but a few large companies. Fabless manufacturers use separate commodity suppliers for wafer fabrication, assembly and test, resulting in poor understanding and control of these key stages of getting a product to market. This has had serious implications for timely product introduction and reliability. Often, a fabless company design team simply handed off good die from their contract foundry to a packaging group or offshore assembler with little thought of reliability. Habits are changing, but the evolution has been very slow. Some new packaging options impose increased mechanical and thermal stresses on the microcircuits, while the low-k dielectrics are considerably weaker than traditional dielectrics. Major reliability hazards include delamination and cracking in the interconnection stack of metals and dielectrics above the active circuitry. Corrosion of metals can also occur after moisture enters through the defective insulation. SEM cross sections will be used to illustrate actual problems that have been observed during structural and failure analyses performed on production devices