Title :
Submicron CMOS MIL-STD-1750A based mission processor
Author :
Coulon, Kenneth E.
Author_Institution :
Texas Instrum., Dallas, TX, USA
Abstract :
The author describes the design of a MIL-STD-1750A mission processor (MP), which is generally based on the US Air Force Pave Pillar architecture. The MP is composed of a power conditioner unit, a chassis assembly, and a set of SEM-E (3/4 ATR)-size common modules. The common modules utilize a set of seven complex submicrometer CMOS integrated circuits as building blocks. The internal design architecture features a dual PI-Bus for intermodule communication and a dual TM-Bus for operational test and maintenance. The MP is capable of over 22-million-instruction/s performance on the Defense Avionics Instructions Set (DAIS) mix and contains up to 2.56 million words of random-access memory and 288 thousand words of read-only memory. The MP provides external interfaces to three dual redundant MIL-STD-1553B serial communication buses, two differential Small Computer System Interface (SCSI) buses, and IEEE-488 bus, and miscellaneous digital and analog discrete lines
Keywords :
CMOS integrated circuits; computer architecture; computer interfaces; military computing; military systems; modules; standards; IEEE-488 bus; MIL-STD-1553B serial communication buses; MIL-STD-1750A mission processor; US Air Force Pave Pillar architecture; common modules; differential Small Computer System Interface; dual PI-Bus; dual TM-Bus; intermodule communication; power conditioner unit; submicrometer CMOS integrated circuits; Built-in self-test; CMOS integrated circuits; CMOS process; Circuit testing; Fault detection; Instruments; Random access memory; Read only memory; Read-write memory; Throughput;
Conference_Titel :
Aerospace and Electronics Conference, 1989. NAECON 1989., Proceedings of the IEEE 1989 National
Conference_Location :
Dayton, OH
DOI :
10.1109/NAECON.1989.40189
