Using Quadded logic in nanoPLAs to aggressively increase circuit yield

Because of the stochastic assembly, nano Programmable Logic Arrays (nanoPLAs) are currently built with a costly test and characterization process. In this paper, we focus on design oriented defect tolerance instead of Physical oriented one, and propose a reliable implementation for nano devices. Our new methodology is based on Quadded NOR logic, which guarantees the circuit function for all single defects and almost all multiple ones. Under Quadded form of design we transfer the costly test and characterization phase in fabrication process of the nanoPLA to a reliable logic design. We use the wrapping feature of nanoPLAs and reduce the overhead of Quadded method on logics in nanoPLA. This feature allows implementation of quadruplicated logic on a nanoPLA by using spared nanowires. This allows design with a very small area overhead. Results show about 100 percent availability of Quadded logic XOR gate implemented on nanoPLAs.