• DocumentCode
    2759148
  • Title

    Reconfigurable, fully scalable integer wavelet transform unit for JPEG2000

  • Author

    Zewail, R. ; Marshall, P. ; Kozicki, S. ; Ying, N. ; Elliott, D. ; Durdle, N.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta.
  • fYear
    2005
  • fDate
    1-4 May 2005
  • Firstpage
    798
  • Lastpage
    801
  • Abstract
    The new still compression image standard, JPEG2000, has emerged with a number of significant features that would allow it to be used efficiently over a wide variety of images. The scalability of this new standard allows trading off between compression rate and quality of image. Due to the multi-resolution nature of wavelet transforms, they have been adopted by the JPEG2000 standard as the transform of choice. In this work, we present an implementation for a re configurable fully scalable integer wavelet transform (IWT) unit that satisfies the specifications of the JPEG2000 standard. The implementation is based on the lifting scheme, which is the most computation efficient implementation of the discrete wavelet transform. Integer wavelet transforms, also known as reversible DWT, have recently received special interest due to a number of significant properties in terms of computational efficiency and storage requirements. The lifting scheme-based integer wavelet transform (IWT) unit was implemented in field programmable gate arrays (FPGAs), namely the Xilinx Vertix II family. The design is scalable in order to allow a trade off between rate and distortion. A maximum clock frequency of 112 MHz, with throughput of over 400 pixels/s, was achieved by employing techniques such as parallel operation of independent units and pipelining. A speed up of over 61 times has been achieved versus a Matlab compiled C code implementation on a Pentium IV 1.8 GHZ processor
  • Keywords
    data compression; discrete wavelet transforms; field programmable gate arrays; image coding; image resolution; FPGA; JPEG2000; Matlab compiled C code; Pentium IV processor; Xilinx Vertix II family; clock frequency; compression rate; discrete wavelet transform; field programmable gate arrays; image quality; image standard; integer wavelet transform unit; lifting scheme; parallel operation; pipelining; reversible DWT; Clocks; Computational efficiency; Discrete wavelet transforms; Field programmable gate arrays; Frequency; Image coding; Rate distortion theory; Scalability; Transform coding; Wavelet transforms;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electrical and Computer Engineering, 2005. Canadian Conference on
  • Conference_Location
    Saskatoon, Sask.
  • ISSN
    0840-7789
  • Print_ISBN
    0-7803-8885-2
  • Type

    conf

  • DOI
    10.1109/CCECE.2005.1557049
  • Filename
    1557049