60 GHz on-chip patch antenna integrated in a 0.13-µm CMOS technology

This paper presents a design method of on-chip patch antenna integration in a standard CMOS technology without post processing. A 60 GHz on-chip patch antenna is designed utilizing the top metal layer and an intermediate metal layer as the patch and ground plane, respectively. Interference between the patch and digital baseband circuits located beneath the ground plane is analyzed. The 60 GHz on-chip antenna occupies an area of 1220 μm by 1580 μm with carefully placed fillers and slots to meet the design rules of the CMOS process. The antenna is centered at 60.51 GHz with 810 MHz bandwidth. The peak gain and radiation efficiency are -3.32 dBi and 15.87%, respectively. Analysis for mutual signal coupling between the antenna and the clock H-tree beneath the ground plane is reported, showing a -61 dB coupling from the antenna to the H-tree and a -95 dB coupling of 2 GHz clock signal from the H-tree to the antenna.