Detectability analysis for resistive open faults with dynamic supply voltage scaling awareness

Dynamic supply voltage scaling (DVS) is an efficient and practical design technique to reduce power consumption in VLSI devices. Due to the multiple voltage operating environment and the supply voltage dependent behavior of physical faults, obtaining a minimal test set which gives the best fault coverage is challenging. Researchers have showed that testing of resistive opens is best achieved at high supply voltage. However based on our experimental results on ISCAS-85 circuits it is shown that is not always the case for DVS enabled designs. This paper analyzes and identifies different detectability patterns for resistive open faults in such designs. Additionally it discussed the multi-VDD testing and its necessity to achieve 100% fault coverage.