Optimization of arsenic and phosphorus Source/Drain implantation for low power NMOS device

In low leakage MOS device fabrication, careful pn junction design is critical to control overall device leakage, such as Band-To-Band Tunneling (BTBT) and Gate-Induced Drain Leakage (GIDL) that are always taken into consideration by device designers. Source/Drain implantation also play a very important role in suppressing silicon dislocation effect, which increases implanted species transient-enhanced diffusion (TED) and induces shallow-junction leakage. In this paper, we describe and analyze optimization works on arsenic and phosphorus Source/Drain implantation for 1.5V low power NMOS in a 0.13um technology. Optimized condition of the Source/Drain implantation can suppress dislocation defect which affects 1.5V NMOS off-state leakage current. By implementing the optimized condition, we improved the 1.5V NMOS off-state leakage current by 65.4%, and achieved higher junction breakdown. Furthermore, device characterization gave robust integrated circuit operation speed.