Process algebra techniques for verification of SDL-diagrams

The authors show how techniques from process algebra can be profitably applied to verification of SDL-diagrams stemming from real life applications in the area of communication protocols. The advantage gained is a speed-up of the development cycle. Instead of searching for errors in the testing phase only the authors´ verification aims at the design phase and thus cuts short the development cycle. A second advantage is higher confidence in the correctness of the system. They assume that the design is made by means of diagrams of the CCITT language SDL (specification and description language). The authors believe that only on the design level the systems are sufficiently abstract and concise to be amenable to formal verification