DocumentCode
2760391
Title
It´s about the power: An architect´s view of interconnect
Author
Dally, Bill
Author_Institution
Stanford Univ., Stanford, CA, USA
fYear
2012
fDate
4-6 June 2012
Firstpage
1
Lastpage
1
Abstract
Summary form only given. As integrated circuit technology scales chips are becoming power, not area limited, and the power dissipated moving bits on, off, and across chips is becoming increasingly important. This talk gives an architect´s perspective on future chip interconnect. The demand for interconnect is driven by the application. Both SoCs and high-performance processors have demanding interconnect requirements. In modern chips, these requirements are met by organizing global interconnect as a network-on-chip or NoC. The regularity afforded by this organization enables layout and circuit optimizations. To reduce the energy per bit-mm, low-energy signaling with sophisticated circuits are becoming more widely used. It is important to optimize the entire interconnect system - the wire, the circuit, and the NoC together - not just each of the three in isolation.
Keywords
integrated circuit interconnections; integrated circuit layout; microprocessor chips; network-on-chip; optimisation; wires (electric); NoC; SoC; circuit optimization; energy per bit-mm reduction; high-performance processor; integrated circuit technology scales chip; layout optimization; low-energy signaling; network-on-chip; power dissipation; wire; Educational institutions; Integrated circuit interconnections; Integrated circuit technology; Organizations; Organizing; Program processors; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Interconnect Technology Conference (IITC), 2012 IEEE International
Conference_Location
San Jose, CA
ISSN
pending
Print_ISBN
978-1-4673-1138-0
Electronic_ISBN
pending
Type
conf
DOI
10.1109/IITC.2012.6251592
Filename
6251592
Link To Document