Runtime Reconfigurable MPSoC architecture for control drive system

Author

Abdelkrim, Hedi ; Ben Othman, Slim ; Ben Salem, Ahmed Karim ; Ben Saoud, Slim

Author_Institution

LECAP EPT, Carthage Univ., Tunis, Tunisia

fYear

2011

fDate

27-30 June 2011

Firstpage

820

Lastpage

825

Abstract

In this paper, an overview of reconfigurability is presented with some design recommendations. Besides, a design flow of a Reconfigurable System on Chip (RSoC) is studied for an application case: the implementation of two different controllers on Multiprocessor SoC (MPSoC) architecture using the FPGA Virtex-II Pro. A runtime partial reconfiguration is adopted to switch between them. A predictive internal state definition allows a soft commutation between controllers. Experimental results confirm the adopted approach efficiency and give satisfying performance.

Keywords

field programmable gate arrays; multiprocessing systems; reconfigurable architectures; system-on-chip; FPGA Virtex-II Pro; control drive system; multiprocessor SoC architecture; predictive internal state definition; reconfigurable system on chip; runtime reconfigurable MPSoC architecture; Computer architecture; Field programmable gate arrays; Hardware; Motor drives; Program processors; Random access memory; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Industrial Electronics (ISIE), 2011 IEEE International Symposium on

Conference_Location

Gdansk

ISSN

Pending

Print_ISBN

978-1-4244-9310-4

Electronic_ISBN

Pending

Type

conf

DOI

10.1109/ISIE.2011.5984264

Filename

5984264