How to half the latency of IEEE compliant floating-point multiplication

We present an IEEE compliant floating-point multiplier that computes the correctly rounded result for all representable floating-point values. This multiplier can be implemented in 2 clock cycles, whenever its adder tree fits in one clock cycle. For the same operation recent multiplier designs need at least 4 clock cycles including the pre and postprocessing for denormalized operands and multistep rounding for the support of different precisions. Our multiplier operates on an internal format that we introduce before. We discuss the changes that become necessary by the use of this format and the optimizations that are possible for the other arithmetic operations