Efficient high-speed CMOS design by layout based schematic method

As the diffusion area and the wire capacitance worsen the circuit performance in very high speed CMOS design, the results between schematic and layout differ from each other because of missing parasitic components in the schematic. We address a layout based schematic (LBS) method for high speed CMOS cell design. In our method, we introduce different types of MOS transistors and a wire capacitance estimation method, based on layout knowledge. The simulation results at very high speed show that the difference between LBS and real circuit layout is much smaller, less than 3 percent in rise time, compared to the difference in the worst case up to 65 percent in original schematic. The result of LBS is reliable and easy to be optimized during the schematic procedure. It will reduce the design time and cost in high speed circuit design. We also believe that the LBS is more convenient to be translated into the real layout than the original schematic