Multi-stage parallel processing of design element access tasks in FPGA-based logic emulation systems

In FPGA based logic emulation systems, effective verification performance not only depends on the frequency at which the design clocks can be advanced, but also on the efficiency of various design element access tasks initiated by associated SW applications like high level testbench, GUI etc. Although existing emulation systems achieve high degree of parallelism in model execution by partitioning the design into multiple FPGAs, the design element access tasks are typically executed sequentially, resulting in suboptimal performance. A multi-stage parallel execution framework for such tasks is presented in this paper. To achieve fine grain parallelism, each task is conceptually decomposed into subtasks for SW processing and HW access, and similar subtasks of multiple tasks are parallelized independently. At SW level, multi-threading of SW processing jobs takes advantage of increasing availability of multi-core processors. Multi-FPGA parallelism is achieved for HW access, to harness independent processing capabilities of a design partition. At a single FPGA level, lazy access mechanism is introduced for parallel processing of multiple HW access tasks, using design specific signal dependency characteristics. The system has been implemented on an industry standard logic emulation system and benchmarks on real designs have shown significant gain in verification performance, while maintaining functional fidelity.