Title :
Metal-Oxide-Semiconductor Devices on GaAs with High-k Dielectric and MOCVD Grown ZnO Interface Passivation Layer
Author :
Kundu, Souvik ; Banerji, Pallab
Author_Institution :
Mater. Sci. Centre, Indian Inst. of Technol. Kharagpur, Kharagpur, India
Abstract :
We report fabrication of GaAs metal-oxide- semiconductor devices with an unpinned interface for improved electrical performance. An ultrathin (~1.8 nm) interface passivation layer (IPL) of ZnO, on GaAs, grown by metal organic chemical vapor deposition prior to the high-k deposition, is proposed to solve the issue of interface pinning. X-ray photoelectron spectroscopy and high-resolution transmission electron microscopy results show that an ultra thin layer of ZnO IPL can effectively suppress the oxides formation and minimize the Fermi level pinning at the interface between the GaAs and TiO2. The advantage of GaAs passivation with MOCVD grown ZnO is demonstrated with very small hysteresis, 2 - 4% frequency dispersion per decade at accumulation capacitance, and a midgap interface trap density as low as 2.5×1011 cm-2 eV-1 determined by full conductance method. The capacitance-voltage (C-V), current density-voltage (J-V) characteristics and charge trapping behavior of the films under constant voltage stressing exhibit an excellent interface quality and high dielectric reliability making the device suitable for advanced complementary metal-oxide-semiconductor (CMOS) and microelectronic applications.
Keywords :
CMOS integrated circuits; Fermi level; III-V semiconductors; MIS devices; MOCVD; X-ray photoelectron spectra; capacitance; gallium arsenide; high-k dielectric thin films; passivation; titanium compounds; transmission electron microscopy; zinc compounds; C-V characteristics; CMOS; Fermi level pinning; GaAs; IPL; J-V characteristics; MOCVD grown interface passivation layer; TiO2; X-ray photoelectron spectroscopy; ZnO; accumulation capacitance; capacitance-voltage characteristics; charge trapping behavior; complementary metal-oxide-semiconductor; constant voltage stressing exhibit; current density-voltage characteristics; dielectric reliability; electrical performance; frequency dispersion per decade; full conductance method; high-k deposition; high-k dielectric passivation layer; high-resolution transmission electron microscopy; interface pinning; interface quality; metal organic chemical vapor deposition; metal-oxide-semiconductor devices; microelectronic applications; midgap interface trap density; ultra thin layer; ultrathin interface passivation layer; unpinned interface; Gallium arsenide; High K dielectric materials; Hysteresis; Logic gates; MOS devices; Passivation; Zinc oxide;
Conference_Titel :
Nanoscience, Technology and Societal Implications (NSTSI), 2011 International Conference on
Conference_Location :
Bhubaneswar
Print_ISBN :
978-1-4577-2035-2
DOI :
10.1109/NSTSI.2011.6111800