• DocumentCode
    2761628
  • Title

    FPGA-Based Design and Implementation of Reduced AES Algorithm

  • Author

    Jun, Yang ; Jun, Ding ; Na, Li ; Yixiong, Guo

  • Author_Institution
    Sch. of Inf. Sci. & Eng., Yunnan Univ., Kunming, China
  • Volume
    2
  • fYear
    2010
  • fDate
    6-7 March 2010
  • Firstpage
    67
  • Lastpage
    70
  • Abstract
    This paper introduces the principle of AES algorithm and the detailed description and implementation on FPGA. This system aims at reduced hardware structure. Compared with the pipeline structure, it has less hardware resources and high cost-effective. And this system has high security and reliability. This AES system can be widely used in the terminal equipments.
  • Keywords
    Algorithm design and analysis; Cryptography; Data security; Design engineering; Field programmable gate arrays; Hardware design languages; Information science; NIST; Pipelines; Throughput; AES; FPGA; Reduced structure; Verilog HDL;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Challenges in Environmental Science and Computer Engineering (CESCE), 2010 International Conference on
  • Conference_Location
    Wuhan, China
  • Print_ISBN
    978-0-7695-3972-0
  • Electronic_ISBN
    978-1-4244-5924-7
  • Type

    conf

  • DOI
    10.1109/CESCE.2010.123
  • Filename
    5493227
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2761628