Low-k interconnect stack with metal-insulator-metal capacitors for 22nm high volume manufacturing

Author

Ingerly, D. ; Agrawal, A. ; Ascazubi, R. ; Blattner, A. ; Buehler, M. ; Chikarmane, V. ; Choudhury, B. ; Cinnor, F. ; Ege, C. ; Ganpule, C. ; Glassman, T. ; Grover, R. ; Hentges, P. ; Hicks, J. ; Jones, D. ; Kandas, A. ; Khan, H. ; Lazo, N. ; Lee, K.S. ;

Author_Institution

Logic Technol. Dev., Intel Corp., Hillsboro, OR, USA

fYear

2012

fDate

4-6 June 2012

Firstpage

1

Lastpage

3

Abstract

We describe interconnect features for Intel´s 22nm high-performance logic technology, with metal-insulator-metal capacitors and nine layers of interconnects. Metal-1 through Metal-6 feature a new ultra-low-k carbon doped oxide (CDO) and a low-k etch stop. Metal-7 and Metal-8 use a low-k CDO. New materials and process optimization provide 13-18% capacitance improvement. Single-exposure patterning for 80nm pitch layers makes the process cost-effective.

Keywords

MIM devices; capacitors; carbon; low-k dielectric thin films; metallisation; optimisation; oxygen; Intel high-performance logic technology; O:C; high volume manufacturing; low-k CDO; low-k interconnect stack; metal-insulator-metal capacitors; single-exposure patterning; size 22 nm; size 80 nm; Capacitance; Dielectrics; Integrated circuit interconnections; MIM capacitors; Metals; Resistance; Stress;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference (IITC), 2012 IEEE International

Conference_Location

San Jose, CA

ISSN

pending

Print_ISBN

978-1-4673-1138-0

Electronic_ISBN

pending

Type

conf

DOI

10.1109/IITC.2012.6251663

Filename

6251663