Title :
56nm-pitch low-k/Cu dual-damascene interconnects integration with sidewall image transfer (SIT) patterning scheme
Author :
Tagami, M. ; Shimada, K. ; Yin, Y. ; Ishikawa, M. ; Waskiewicz, C. ; Chen, S-T ; Shobha, H. ; Soda, E. ; Saulnier, N. ; Arnold, J.C. ; Colburn, M. ; Usui, T. ; Spooner, T.
Author_Institution :
Renesas Electron., Albany, NY, USA
Abstract :
Three metal level 56nm-pitch Cu dual damascene interconnects in k2.7 low-k ILD have been demonstrated by using sidewall-image-transfer (SIT) patterning scheme to investigate the feasibility of the SIT process for sub 50nm-pitch technology node. 45nm-pitch line resistance (R) and capacitance (C) simulation are performed to estimate the R-C variation for double patterning schemes. The photoresist mandrel SIT process for 56nm-pitch Cu line is investigated to develop the constant line pitch and less line edge roughness (LER). The basic electrical properties such as line open/short and via chain open/short yields are ~100%. The 56nm-pitch R-C variation is comparable to simulated 80nm-pitch R-C variation. The SIT patterning process is a strong candidate to improve the R-C variation for sub50nm-pitch technology nodes.
Keywords :
RC circuits; copper; integrated circuit interconnections; photoresists; Cu; R-C variation; SIT patterning scheme; chain open-short yield; constant line pitch; double patterning scheme; electrical property; less LER; less line edge roughness; line capacitance simulation; line open-short yield; line resistance simulation; low-k ILD; low-k-Cu dual-damascene interconnection integration; photoresist mandrel SIT process; sidewall image transfer patterning scheme; size 45 nm; size 50 nm; size 56 nm; size 80 nm; three metal level dual damascene interconnection; Capacitance; Lithography; Resistance; Resists; Smoothing methods; Tin;
Conference_Titel :
Interconnect Technology Conference (IITC), 2012 IEEE International
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4673-1138-0
Electronic_ISBN :
pending
DOI :
10.1109/IITC.2012.6251664
