MHERTZ: a new optimization algorithm for floorplanning and global routing

Author

Brasen, Daniel R. ; Bushnell, Michael L.

Author_Institution

VLSI Technol. Inc., San Jose, CA, USA

fYear

1990

fDate

24-28 Jun 1990

Firstpage

107

Lastpage

110

Abstract

Timing-driven placement is essential for full-custom VLSI, gallium arsenide, and ECL circuits to meet wire timing constraints. A new macro/custom cell floorplanner and global router, called MHERTZ, is described. It meets wire timing constraints by using force-directed cost functions in multistart and simulated annealing (SA) optimization algorithms. MHERTZ also prevents wire coupling, meets specified chip aspect ratios, and produces smaller floorplans than TIMBERWOLFMC

Keywords

VLSI; circuit layout CAD; emitter-coupled logic; optimisation; ECL circuits; chip aspect ratios; floorplanning; force-directed cost functions; full-custom VLSI; global routing; optimization algorithm; simulated annealing; wire timing constraints; Circuit simulation; Cost function; Force measurement; Integrated circuit interconnections; Pins; Routing; Simulated annealing; Timing; Very large scale integration; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1990. Proceedings., 27th ACM/IEEE

Conference_Location

Orlando, FL

ISSN

0738-100X

Print_ISBN

0-89791-363-9

Type

conf

DOI

10.1109/DAC.1990.114838

Filename

114838

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2761928