DocumentCode
2762389
Title
Enhanced delay defect coverage with path-segments
Author
Sharma, Mukesh ; Patel, Janak H.
Author_Institution
Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
fYear
2000
fDate
2000
Firstpage
385
Lastpage
392
Abstract
The number of robustly testable paths is very low for typical circuits, hence the delay defect coverage of a robust path fault test set can be very small. Robustly testing path-segments which are not covered by any robustly testable paths can enhance the defect coverage of a path test set, however the existence of such uncovered path-segments in benchmark circuits has not been proven so far. In this paper we experimentally prove the existence of robustly testable path-segments not covered by any robustly testable paths in the ISCAS benchmark circuits. A highly effective delay fault test generator using some novel techniques, has been implemented for this purpose and is also described in the paper
Keywords
automatic test pattern generation; combinational circuits; delays; digital integrated circuits; fault location; integrated circuit testing; integrated logic circuits; logic testing; sequential circuits; ATPG tool; ISCAS benchmark circuits; delay fault test generator; enhanced delay defect coverage; path-segments; robust path fault test set; robustly testable paths; Benchmark testing; Circuit faults; Circuit testing; Context modeling; Contracts; Delay; Electrical fault detection; Fault detection; High performance computing; Robustness;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2000. Proceedings. International
Conference_Location
Atlantic City, NJ
ISSN
1089-3539
Print_ISBN
0-7803-6546-1
Type
conf
DOI
10.1109/TEST.2000.894228
Filename
894228
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