Generation of regular logic cell structures for coding in real-time optical CDMA network

System generator from Xilinx is a powerful hardware design tool based on Matlab/Simulink environment that enables fast creation of easy to understand and clear visual designs. Nevertheless, automatic generation of regular structures, which is possible in languages such as VHDL or Verilog by using the "generate" statement, is not possible in system generator without custom scripts. This paper presents the design of a generate block for system generator that allows automatic creation of regular cells of logic and regular interconnects of these cells based on external parameters. We describe the design methodology using our generate block that enables design time customizability of structures for various arrangements (linear arrays, matrices, trellises or trees). Finally, we employing our generate block in the development of real-time forward error correcting codes for an overloaded optical CDMA network transmission. The generate block effectively parallelizes operations, such as matrix multiplication, computation of a stage of the Viterbi or BCJR algorithm employed in decoding of a block or convolutional code. It allows running FEC decoders at the required high speeds, while allowing these algorithms to be fully design time customizable