DocumentCode
2762521
Title
Design-for-test methods for stand-alone SRAMs at 1 Gb/s/pin and beyond
Author
Pilo, Harold ; Hall, Stu ; Hansen, Patrick ; Lamphier, Steve ; Murphy, Chris
Author_Institution
Microelectron. Div., IBM Corp., Essex Junction, VT, USA
fYear
2000
fDate
2000
Firstpage
436
Lastpage
443
Abstract
Design-for-test techniques for wafer test, component test and system-level diagnostics are implemented on standalone SRAMs at 1 Gb/s/pin. These design-for-test techniques achieve several objectives: improved tester measurement accuracy, higher component yield, and optimal system-level SRAM performance
Keywords
CMOS memory circuits; SRAM chips; automatic testing; design for testability; integrated circuit testing; logic testing; 1 Gbit/s; DFT techniques; component test; component yield improvement; design-for-test methods; optimal system-level SRAM performance; stand-alone SRAMs; static RAM chips; system-level diagnostics; tester measurement accuracy improvement; wafer test; Circuit testing; Clocks; Control systems; Design for testability; Frequency; Random access memory; Semiconductor device measurement; System testing; System-on-a-chip; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2000. Proceedings. International
Conference_Location
Atlantic City, NJ
ISSN
1089-3539
Print_ISBN
0-7803-6546-1
Type
conf
DOI
10.1109/TEST.2000.894235
Filename
894235
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