AMULET3 revealed

Author

Garside, J.D. ; Furber, S.B. ; Chung, S.-H.

Author_Institution

Dept. of Comput. Sci., Manchester Univ., UK

fYear

1999

fDate

1999

Firstpage

51

Lastpage

59

Abstract

AMULET3 is the third fully asynchronous implementation of the ARM architecture designed at the University of Manchester. It implements the most recent version of the ARM architecture (v4T), including the Thumb instruction set. Significant architectural changes from its predecessors help achieve higher performance without sacrificing the advantages of asynchronous design and some new power-saving features have been incorporated. This paper outlines the AMULET3 microprocessor core, highlighting where this design differs from its predecessors. Most notable among the changes are the use of a Harvard architecture to increase memory bandwidth and the inclusion of a recorder buffer to handle data forwarding and memory faults

Keywords

asynchronous sequential logic; computer architecture; instruction sets; microprocessor chips; AMULET3; ARM architecture; Harvard architecture; Thumb instruction set; data forwarding; fully asynchronous implementation; memory bandwidth; memory faults; microprocessor core; power-saving features; recorder buffer; Asynchronous circuits; Bandwidth; Circuit faults; Computer science; Latches; Microprocessors; Pipelines; Prefetching; Read only memory; Thumb;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Research in Asynchronous Circuits and Systems, 1999. Proceedings., Fifth International Symposium on

Conference_Location

Barcelona

ISSN

1522-8681

Print_ISBN

0-7695-0031-5

Type

conf

DOI

10.1109/ASYNC.1999.761522

Filename

761522