Onmitigating power and delay in VLSI interconnects

Long interconnects in very large scale integration (VLSI) circuits result in high delays and power dissipation, thereby degrading the performance of an integrated circuit. The feasibilities of minimizing both delay and power dissipation in long interconnects by insertion of voltage-scaled repeaters have been explored in this paper. The results show a decrease in optimum number of repeaters with voltage-scaling, resulting in reduction of silicon area consumed and lesser heating of the chip. The analytical results for delay have been verified using SPICE simulations and a good agreement between the two has been observed. The simulation results for 0.8 mum and 0.18 mum CMOS technologies have been given