HDL2GDS: a fully automated ASIC digital design flow

HDL2GDS is a fully automated ASIC digital design flow capable of transforming VHDL or Verilog integrated circuit specifications into a corresponding GDSII mask layout file. With one command the RTL or behavioral-level HDL specification is synthesized, a simple floorplan is generated, blocks and macros are placed, power is routed, standard cells are placed, a clock-tree is generated, hold-time violations are detected and fixed, routing is performed, a manufacturing logo is added, IO pads are attached, the GDSII mask layout is exported and finally DRC & LVS and static timing analysis are performed. The flow incorporates the following tools, made available by the Canadian Microelectronics Corporation: Synopsys Design Compiler and PrimeTime, Cadence First Encounter and DFII, and Mentor Graphics Calibre. HDL2GDS is fully customizable with respect to capability and target libraries through the use of tool-scripts and a single design configuration file. The flow generates a GDSII mask layout for a 360 K gate communications chip within 30 hours on a Sun Fire V880 with 12 GB of memory. After much development effort the flow´s ease of use is now comparable to FPGA synthesis. We discuss the limitations of the flow, the difficulties encountered when creating an automated digital design flow and maintenance challenges