Design and implementation of a parallel automatic test pattern generation algorithm with low test vector count

Author

Butler, Robert ; Keller, Brion ; Paliwal, Sarala ; Schoonover, Richard ; Swenton, Joseph

Author_Institution

Microelectron. Div., IBM Corp., Endicott, NY, USA

fYear

2000

fDate

2000

Firstpage

530

Lastpage

537

Abstract

We present an implementation for parallel ATPG that is constructed so as to achieve a test vector count comparable to the serial algorithm. This task posed a challenge since, unlike previous published works, substantial effort is applied in the serial algorithm to keep the test vector count low. Results on industrial circuits that range in size from 700000 gates to about 3 million gates are presented. Previous works have published results for smaller circuits

Keywords

automatic test pattern generation; fault simulation; parallel algorithms; parallel architectures; resource allocation; ASIC; algorithm design; fault simulation; implementation; industrial circuits; load balancing; low test vector count; parallel ATPG algorithm; parallel architecture; partitioning; pattern count; redundancy; Algorithm design and analysis; Application specific integrated circuits; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit simulation; Circuit testing; Compaction; Performance evaluation; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2000. Proceedings. International

Conference_Location

Atlantic City, NJ

ISSN

1089-3539

Print_ISBN

0-7803-6546-1

Type

conf

DOI

10.1109/TEST.2000.894246

Filename

894246